1. Field of the Invention
The present invention relates to a solid-state imaging apparatus using an amplification-type MOS sensor for amplifying signal charges within cells.
2. Discussion of the Background
Recently, compact video cameras and high-resolution, high-vision solid-state imaging apparatuses have been developed. Strong demands have arisen for not only compact cameras and solid-state imaging apparatuses but also low-power-consumption, low-voltage solid-state imaging apparatuses as portable cameras and personal computer cameras.
As the chip size of a solid-state imaging apparatus decreases, however, the amount of signal charge to be processed decreases due to micropatterning. As a result, the dynamic range of the solid-state imaging apparatus narrows, and hence a clear, high-resolution video cannot be obtained. In addition, since many power supply voltages having two, three, or more values are used, a simple system cannot be coped with in terms of camera system configuration and handling. That is, for application to portable cameras and personal computer cameras, a solid-state imaging apparatus which attains a high S/N ratio and uses a single power supply, and also attains reductions in power consumption and voltage is required.
To solve this problem, several amplification-type solid-state imaging apparatuses using transistors have been proposed. These solid-state imaging apparatuses are designed to cause transistors to amplify signals detected by photodiodes in the respective cells, and are characterized by having a high sensitivity.
FIG. 1 is a circuit diagram showing the arrangement of a conventional solid-state imaging apparatus using an amplification-type MOS sensor. Unit cells P0-i-j are arranged in the form of a two-dimensional matrix. Although FIG. 1 shows only a 2.times.2 matrix, the actual apparatus has several thousand cells.times.several thousand cells. Reference symbol i denotes a variable in the horizontal (row) direction; and j, a variable in the vertical (column) direction. Each unit cell P0-i-j is constituted by a photodiode 1-i-j for detecting incident light, an amplification transistor 2-i-j having a gate to which the cathode of the photodiode 1-i-j is connected and designed to amplify the detection signal, a vertical selection transistor 3-i-j connected to the drain of the amplification transistor 2-i-j to select a horizontal line for reading out the signal, and a reset transistor 4-i-j connected to the cathode of the photodiode 1-i-j to reset the signal charge. The source of the vertical selection transistor 3-i-j and the source of the reset transistor 4-i-j are commonly connected to a drain voltage terminal.
Vertical address lines 6-1, 6-2, . . . horizontally extending from a vertical address circuit 5 are connected to the gates of vertical selection transistors 3-1-1, . . . of the unit cells in the respective rows to determine horizontal lines for reading out signals. Similarly, reset lines 7-1, 7-2, . . . horizontally extending from the vertical address circuit 5 are connected to the gates of reset transistors 4-1-1, . . . in the respective rows.
The sources of amplification transistors 2-1-1, . . . of the unit cells in the respective rows are connected to vertical signal lines 8-1, 8-2, . . . arranged in the column direction. Each of load transistors 9-1, 9-2, . . . is connected to one end of a corresponding one of the vertical signal lines 8-1, 8-2, . . . A signal output terminal (horizontal signal line) 15 is connected to the other end of each of the vertical signal lines 8-1, 8-2, . . . through horizontal selection transistors 12-1, 12-2, . . . which are driven by horizontal address pulses output from a horizontal address circuit 13.
The operation of this device will be described with reference to a timing chart shown in FIG. 2.
When a high-level address pulse is applied to the vertical address line 6-i, only the vertical selection transistors 3-i-1, 3-i-2, . . . in this line are turned on. As a result, source follower circuits are constituted by the amplification transistors 2-i-1, 2-i-2, . . . and the load transistors 9-i-1, 9-i-2, . . . in this line.
With this operation, the gate voltages of the amplification transistors 2-i-1, 2-i-2, . . . , i.e., almost the same voltages as those of the photodiodes 1-i-1, 1-i-2, . . . , appear on the vertical signal lines 8-i-1, 8-i-2, . . .
When a signal transfer pulse is applied to a common gate 14 of signal transfer transistors 10-1, 10-2, . . . , an amplified signal charge corresponding to a product of voltages appears on the vertical signal lines 8-i-1, 8-i-2, . . . and their capacitances appear on amplified signal storage capacitors 11-1, 11-2, . . .
After the signal charges are stored in the amplified signal storage capacitors 11-1, 11-2, . . . and the signal transfer transistors 10-1, 10-2, . . . are turned off, reset pulses are applied to the reset lines 7-1, 7-2, . . . to turn off the reset transistors 4-i-1, 4-i-2, . . . With this operation, the signal charges stored in the photodiodes 1-i-1, 1-i-2, . . . are reset.
Horizontal address pulses are sequentially applied from the horizontal address circuit 13 to the horizontal selection transistors 12-1, 12-2, . . . to sequentially output signals corresponding to lines (rows) from the signal output terminal 15.
By sequentially performing this operation for the subsequent lines, all the signals in the two-dimensional matrix can be read out.
Each unit cell P0-i-j in a solid-state imaging apparatus using an amplification-type MOS sensor of this type, requires at least three transistors, i.e., the amplification transistor 2-i-j for amplifying a charge signal from the photodiode 1-i-j, the vertical selection transistor 3-i-j for selecting a line to read a signal, and the reset transistor 4-i-j for charging/discharging the gate of the amplifying transistor. Therefore, it is difficult to miniaturize the unit cell and the imaging device itself.